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ds090 (v3.1) september 11, 2008 www.xilinx.com 1 product specification ? 2002?2008 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? optimized for 1.8v systems - industry?s fastest low power cpld - densities from 32 to 512 macrocells ? industry?s best 0.18 micron cmos cpld - optimized architecture fo r effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3.3v ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - on-the-fly reconfiguration (otf) - ieee1149.1 jtag boundary scan test - optional schmitt trigger input (per pin) - multiple i/o banks on all devices - unsurpassed low power management datagate external signal control - flexible clocking modes optional dualedge triggered registers clock divider ( 2,4,6,8,10,12,14,16) coolclock - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - abundant product term clocks, output enables and set/resets - efficient control term clocks, output enables and set/resets for each macroc ell and shared across function blocks - advanced design security - open-drain output option for wired-or and led drive - optional bus-hold, 3-state or weak pullup on select i/o pins - optional configurable grounds on unused i/os - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels on all parts - sstl2_1,sstl3_1, and hstl_1 on 128 macrocell and denser devices - hot pluggable ? pla architecture - superior pinout retention - 100% product term routability across function block ? wide package availability including fine pitch: - chip scale package (csp) bga, fine line bga, tqfp, pqfp, vqfp, and qfn packages - pb-free available for all packages ? design entry/verification using xilinx and industry standard cae tools ? free software support for all densities using xilinx? webpack? tool ? industry leading nonvolatile 0.18 micron cmos process - guaranteed 1,000 program/erase cycles - guaranteed 20 year data retention family overview xilinx coolrunner?-ii cplds deliver the high speed and ease of use associated with the xc9500/xl/xv cpld fam- ily with the extremely low power versatility of the xpla3 family in a single cpld. this means that the exact same parts can be used for high-speed data communications/ computing systems and leading edge portable products, with the added benefit of in system programming. low power consumption and high-speed operation are com- bined into a single family that is easy to use and cost effec- tive. clocking techniques and other power saving features extend the users? power budget. the design features are supported starting with xilinx ise? 4.1i webpack tool. additional details can be found in further reading , page 14 . ta b l e 1 shows the macrocell capacity and key timing parameters for the coolrunner-ii cpld family. 0 coolrunner-ii cpld family ds090 (v3.1) september 11, 2008 00 product specification r ta bl e 1 : coolrunner-ii cpld family parameters xc2c32a xc2c64a xc2c128 xc2c256 xc2c384 XC2C512 macrocells 32 64 128 256 384 512 max i/o 33 64 100 184 240 270 t pd (ns) 3.8 4.6 5.7 5.7 7.1 7.1 t su (ns) 1.9 2.0 2.4 2.4 2.9 2.6 t co (ns) 3.7 3.9 4.2 4.5 5.8 5.8 f system1 (mhz) 323 263 244 256 217 179
coolrunner-ii cpld family 2 www.xilinx.com ds090 (v3.1) september 11, 2008 product specification r ta bl e 2 shows key dc characteristics for the coolrunner-ii family. ta bl e 3 shows the coolrunner-ii cpld package offering with corresponding i/o count. all packages are surface mount, with over half of them being ball-grid technologies. the ultra tiny packages permit maximum functional capacity in the smallest possible area. the cmos technology used in coolrunner-ii cplds generates minimal heat, allowing the use of tiny packages during high-speed operation. with the exception of the pb-free qf packages, there are at least two densities present in each package with three in the vq100 (100-pin 1.0mm qfp), tq144 (144-pin 1.4mm qfp), and ft256 (256-ball 1.0mm spacing flbga). the ft256 is particularly important for slim dimensioned porta- ble products with mid- to hi gh-density logic requirements. ta bl e 4 details the distribution of advanced features across the coolrunner-ii cpld family. the family has uniform basic features with advanced features included in densities where they are most useful. for example, it is very unlikely that four i/o banks are needed on 32 and 64 macrocell parts, but very likely they are for 384 and 512 macrocell parts. the i/o banks are groupings of i/o pins using any one of a subset of compatible voltage standards that share ta bl e 2 : coolrunner-ii cpld dc characteristics xc2c32a xc2c64a xc2c128 xc2c256 xc2c384 XC2C512 i cc ( a), 0 mhz, 25c (typical) 16 17 19 21 23 25 i cc (ma), 50 mhz, 70c (max) 2.5 5 10 27 45 55 1. i cc is dynamic current. ta bl e 3 : coolrunner-ii cpld family packages and i/o count xc2c32a xc2c64a xc2c128 xc2c256 xc2c384 XC2C512 qfg32 ( 1 ) 21 - - - - - vq44 33 33 - - - - vqg44 ( 1 ) 33 33 - - - - qfg48 ( 1 ) -37- - -- cp56 33 45 - - - - cpg56 ( 1 ) 33 45 - - - - vq100 - 64 80 80 - - vqg100 ( 1 ) -648080-- cp132 - - 100 106 - - cpg132 ( 1 ) - - 100 106 - - tq144 - - 100 118 118 - tqg144 ( 1 ) - - 100 118 118 - pq208 - - - 173 173 173 pqg208 ( 1 ) - - - 173 173 173 ft256 - - - 184 212 212 ftg256 ( 1 ) - - - 184 212 212 fg324 - - - - 240 270 fgg324 ( 1 ) - - - - 240 270 notes: 1. the letter "g" as the third char acter indicates a pb-free package.
coolrunner-ii cpld family ds090 (v3.1) september 11, 2008 www.xilinx.com 3 product specification r the same v ccio level. (see ta bl e 5 for a summary of coolrunner-ii cpld i/o standards.) architecture description coolrunner-ii cpld is a highly uniform family of fast, low power cplds. the underlying ar chitecture is a traditional cpld architecture combini ng macrocells into function blocks (fbs) interconnected with a global routing matrix, the xilinx advanced interconnec t matrix (aim). the fbs use a programmable logic array (pla) configuration which allows all product terms to be routed and shared among any of the macrocells of the fb. design software can efficiently synthesize and optimize logic that is subsequently fit to the fbs and connected with the ability to utilize a very high per- centage of device resources. design changes are easily and automatically managed by the software, which exploits the 100% routability of the pr ogrammable logic array within each fb. this extremely robu st building block delivers the industry?s highest pinout retention, under very broad design conditions. the architecture is explained in more detail with the discussion of the underlying fbs, logic and intercon- nect. the design software automatically manages these device resources so that users can express their designs using completely generic constructs without knowledge of these architectural details. more advanced users can take advan- tage of these details to more thoroughly understand the software?s choices and direct its results. figure 1 shows the high-level architecture whereby fbs attach to pins and interconnect to each other within the internal interconnect matrix. each fb contains 16 macro- cells. the bsc path is the jtag boundary scan control ta bl e 4 : coolrunner-ii cpld family features xc2c32a xc2c64a xc2c128 xc2c256 xc2c384 XC2C512 ieee 1532 ?????? i/o banks 2 2 2 2 4 4 clock division - - ???? dualedge registers ?????? datagate - - ???? lv t t l ?????? lvcmos33, 25, 18, and 15 ( 1 ) ?????? sstl2_1 - - ???? sstl3_1 - - ???? hstl_1 - - ???? configurable ground ?????? quadruple data security ?????? open drain outputs ?????? hot plugging ?????? schmitt inputs ?????? 1. lvcmos15 requires the use of schmitt-trigger inputs.
coolrunner-ii cpld family 4 www.xilinx.com ds090 (v3.1) september 11, 2008 product specification r path. the bsc and isp block has the jtag controller and in-system programming circuits. function block the coolrunner-ii cpld fbs contain 16 macrocells, with 40 entry sites for signals to ar rive for logic creation and con- nection. the internal logic engine is a 56 product term pla. all fbs, regardless of the number contained in the device, are identical. for a high-level view of the fb, see figure 2 . at the high level, the product terms (p-terms) reside in a programmable logic array (pla). this structure is extremely flexible, and very robust when compared to fixed or cas- caded product term fbs. classic cplds typically have a few product terms available for a high-speed path to a given macrocell. they rely on capturing unused p-terms from neighboring macrocells to expand their product term tally, when needed. the result of this architecture is a variable timing model and the possibil- ity of stranding unusable logic within the fb. the pla is different ? and better. first, any product term can be attached to any or gate inside the fb macrocell(s). second, any logic function can have as many p-terms as needed attached to it within the fb, to an upper limit of 56. third, product terms can be re-used at multiple macrocell or functions so that within a fb , a particular logical product need only be created once, but can be re-used up to 16 times within the fb. naturally, this plays well with the fitting software, which identifies product terms that can be shared. the software places as many of those functions as it can into fbs, so it happens for free. there is no need to force macrocell functions to be adjacent or any other restriction save residing in the same fb, which is handled by the soft- ware. functions need not share a common clock, common set/reset, or common output enable to take full advantage of the pla. also, every product term arrives with the same time delay incurred. there are no cascade time adders for putting more product terms in the fb. when the fb product term budget is reached, there is a small interconnect timing penalty to route signals to another fb to continue creating logic. xilinx design software h andles all this automatically. figure 1: coolrunner-ii cpld architecture function block 1 function block n pla pla i/o blocks i/o blocks 16 16 40 40 16 fb 16 fb 16 16 i/o pin mc1 mc2 mc16 mc1 mc2 mc16 ds090_01_121201 aim i/o pin i/o pin direct inputs bsc and isp clock and control signals bsc path direct inputs i/o pi n i/o pi n i/o pi n jtag figure 2: coolrunner-ii cpld function block pla 16 40 3 mc1 out to aim global clocks global set/reset mc2 mc16 ds090_02_101001
coolrunner-ii cpld family ds090 (v3.1) september 11, 2008 www.xilinx.com 5 product specification r macrocell the coolrunner-ii cpld macrocell is extremely efficient and streamlined for logic creation. users can develop sum of product (sop) logic expressions that comprise up to 40 inputs and span 56 product terms within a single function block. the macrocell can further combine the sop expres- sion into an xor gate with another single p-term expres- sion. the resulting logic expression?s polarity is also selectable. as well, the logic function can be pure combina- torial or registered, with the storage element operating selectably as a d or t flip-flo p, or transparent latch. avail- able at each macrocell are independent selections of global, function block level or local p-term derived clocks, sets, resets, and output enables. each macrocell flip-flop is con- figurable for either single edge or dualedge clocking, pro- viding either double data rate capability or the ability to distribute a slower clock (thereby saving power). for single edge clocking or latching, either clock polarity can be selected per macrocell. coolrunner-ii cpld macrocell details are shown in figure 3 . note that in figure 4 , stan- dard logic symbols are used except the trapezoidal multi- plexers have input selection from statically programmed configuration select lines ( not shown). xilinx application note xapp376 gives a detailed explanation of how logic is created in the coolrunner-ii cpld family. when configured as a d-type flip-flop, each macrocell has an optional clock enable signal permitting state hold while a clock runs freely. note that control terms (ct) are available to be shared for key functions within the fb, and are gener- ally used whenever the exact same logic function would be repeatedly created at multip le macrocells. the ct product terms are available for fb clocking (ctc), fb asynchro- nous set (cts), fb asynchronous reset (ctr), and fb out- put enable (cte). any macrocell flip-flop can be configured as an input regis- ter or latch, which takes in the signal from the macrocell?s i/o pin, and directly drives the aim. the macrocell combina- tional functionality is retained for use as a buried logic node if needed. f toggle is the maximum clock frequency to which a t flip-flop can reliably toggle. advanced interconnect matrix (aim) the advanced interconnect matrix is a highly connected low power rapid switch. the aim is directed by the software to deliver up to a set of 40 signals to each fb for the cre- ation of logic. results from all fb macrocells, as well as, all pin inputs circulate back through the aim for additional con- nection available to all other fbs as dictated by the design figure 3: coolrunner-ii cpld macrocell gck0 gck1 gck2 ctc ptc ptc ds090_03_121201 49 p-terms to pta, ptb, ptc of other macrocells ctc, ctr, cts, cte from aim 4 p-terms pta direct input from i/o block feedback to aim ptb ptc pla or term pta cts gsr gnd gnd v cc r d/t ce ck fif latch dualedge q s 40 to i/o block pta ctr gsr gnd
coolrunner-ii cpld family 6 www.xilinx.com ds090 (v3.1) september 11, 2008 product specification r software. the aim minimizes both propagation delay and power as it makes attachments to the various fbs. i/o block i/o blocks are primarily transceivers. however, each i/o is either automatically compliant with standard voltage ranges or can be programmed to become so. see xapp382 for detailed information on coolrunner-ii i/os. in addition to voltage levels , each input can selectively arrive through schmitt-trigger inputs. this adds a small time delay, but substantially reduces noise on that input pin. approximately 500 mv of hysteresis is added when schmitt-trigger inputs are se lected. all lvcmos inputs can have hysteresis input. hysteres is also allows easy genera- tion of external clock circuits. the schmitt-trigger path is best seen in figure 4 . see ta b l e 5 for schmitt-trigger com- patibility with i/o standards. outputs can be directly driven, 3-stated or open-drain con- figured. a choice of slow or fast slew rate output signal is also available. ta bl e 5 summarizes various supported volt- age standards associated with specific part capacities. all inputs and disabled outputs are voltage tolerant up to 3.3v. the coolrunner-ii family supports sstl2-1, sstl3-1 and hstl-1 high-speed i/o standards in the 128-macrocell and larger devices. figure 4 details the i/o pin, where it is noted that the inputs requiring comparison to an external refer- ence voltage are available. these i/o standards all require v ref pins for proper operation. the coolrunner-ii cpld allows any i/o pin to act as a v ref pin, granting the board layout engineer extra freedom when laying out the pins. however, if v ref pin placement is not done properly, addi- tional v ref pins might be required, resulting in a loss of potential i/o pins or board re-work. see xapp399 for details regarding v ref pins and their placement. v ref has pin-range requirements that must be observed. the xilinx software aids design ers in remaining within the proper pin range. ta bl e 5 summarizes the single ended i/o standard support and shows which standards require v ref values and board termination. v ref detail is given in specific data sheets. figure 4: coolrunner-ii cpld i/o block diagram enabled to macrocell direct input to aim 4 cte ptb gts[0:3] cgnd open drain from macrocell v ccio v ref disabled hysteresis available on 128 macrocell devices and larger global termination pullup/bus-hold ds090_04_121201 ta bl e 5 : coolrunner-ii cpld i/o standard summary iostandard attribute v ccio input v ref board termination voltage (v tt ) schmitt-trigger support lvttl 3.3 n/a n/a optional lvcmos33 3.3 n/a n/a optional lvcmos25 2.5 n/a n/a optional lvcmos18 1.8 n/a n/a optional lvcmos15 1.5 n/a n/a not optional hstl_1 1.5 0.75 0.75 not optional sstl2_1 2.5 1.25 1.25 not optional sstl3_1 3.3 1.5 1.5 not optional
coolrunner-ii cpld family ds090 (v3.1) september 11, 2008 www.xilinx.com 7 product specification r output banking cplds are widely used as voltage interface translators. to that end, the output pins are grouped in large banks. the xc2c32a, xc2c64a, xc2c128 and xc2c256 devices support two output banks. with two, the outputs switch to one of two selected output voltage levels, unless both banks are set to the same voltage. the larger parts (384 and 512 macrocell) support four output banks split evenly. they can support groupings of one, two, three, or four separate output voltage levels. this kind of fl exibility permits easy interfacing to 3.3v, 2.5v, 1.8v, and 1.5v in a single part. datagate low power is the hallmark of cmos technology. other cpld families use a sense amplifier approach to creating product terms, which always has a residual current compo- nent being drawn. this residual current can be several hun- dred milliamps, making them un usable in portable systems. coolrunner-ii cplds use standard cmos methods to cre- ate the cpld architecture and deliver the corresponding low current consumption, withou t doing any special tricks. however, sometimes designers want to reduce their system current even more by selectively disabling circuitry not being used. the patented datagate technology to permits a straight- forward approach to additional power reduction. each i/o pin has a series switch that can block the arrival of free run- ning signals that are not of interest. signals that serve no use might increase power consumption, and can be dis- abled. users are free to do their design, then choose sec- tions to participate in the datagate function. datagate is a logic function that drives an assertion rail threaded through the medium and high-density coolrunner-ii cpld parts. designers can select inputs to be blocked under the control of the datagate function, effectively blocking con- trolled switching signals so they do not drive internal chip capacitances. output signals that do not switch are held by the bus hold feature. any set of input pins can be chosen to participate in the datagate function. figure 5 shows the familiar cmos i cc versus switching frequency graph. with datagate, designers can approach zero power, should they choose to, in their designs. figure 6 shows how datagate basically works. one i/o pin drives the datagate assertion rail. it can have any desired logic function on it. it can be as simple as mapping an input pin to the datagate function or as complex as a counter or state machine output driving the datagate i/o pin through a macrocell. when the datagate rail is asserted high, any pass transistor switch attached to it is blocked. each pin has the ab ility to attach to the aim through a datagate pass transistor, and thus be blocked. a latch automatically captures the state of the pin when it becomes blocked. the datagate assertion rail threads throughout all possible i/os, so each can participate if cho- sen. note that one macrocell is singled out to drive the rail, and that macrocell is exposed to the outside world through a pin, for inspection. if datagate is not needed, this pin is an ordinary i/o. there are two attributes associated with the datagate fea- ture in coolrunner-ii cplds. the first attribute specifies if an input is affected by datagate and the second desig- nates the datagate control signal. the datagate feature is selectable on a per pin basis. each input pin that uses datagate must be assigned a data_gate attribute. the datagate assertion rail can be driven from either an i/o pin or internal logic. the datagate enable signal is a dedicated dge/i/o pin for each package in coolrunner-ii cplds. upon implementation, the software recognizes a design using datagate and automatically assigns this i/o pin to the datagate enable control function, dge. inter- figure 5: cmos i cc vs. switching frequency curve ds090_05_101001 i cc frequency 0
coolrunner-ii cpld family 8 www.xilinx.com ds090 (v3.1) september 11, 2008 product specification r nally generated datagate control logic can be assigned to this i/o pin with the bufg=data_gate attribute. global signals global signals, clocks (gck), sets/resets (gsr), and output enables (gts), are designed to strongly resemble each other. this approach enables design software to make the best utilization of th eir capabilities. each global capability is supplemented by a corresponding product term version. figure 7 shows the common structure of the global signal trees. the pin input is buffered, then drives multiple internal global signal traces to deliver low skew and reduce loading delays. gck, gsr, and gts can also be used as general purpose i/os if they are not needed as global signals. the datagate assertion rail is also a global signal. figure 6: datagate architecture (output drivers not shown) pla mc1 mc2 mc16 ds090_06_111201 pla pla datagate assertion rail pla aim mc1 mc2 mc16 mc1 mc2 mc16 mc1 mc2 mc16 to aim latch to aim latch to aim to aim latch latch to aim latch figure 7: global clocks (gck), sets/resets (gsr), and output enables (gts) ds090_07_101001
coolrunner-ii cpld family ds090 (v3.1) september 11, 2008 www.xilinx.com 9 product specification r additional clock op tions: division, dualedge, and coolclock clock divider a clock divider circuit has been included in the coolrunner-ii cpld architecture to divide one externally supplied global clock by standard values. the allowable val- ues for the division are 2, 4, 6, 8, 10, 12, 14, and 16 (see figure 8 ). this capability is supp lied on the gck2 pin. the resulting clock produced has a 50% duty cycle for all possi- ble divisions. the output of the clock divider is on global routing. if the clock divider is used, the undivided clock is available internally. if the und ivided clock is required inter- nally it is input through a separate clock pin. the clock divider circuit encompasses a synchronous reset (cdrst) to guarantee no spurious clocks can carry through on to the global clock nets. when the cdrst signal is asserted, the clock divider output is disabled after the cur- rent cycle. when the cdrst signal is deasserted the clock divider output becomes active upon the first edge of gck2. the cdrst pin functions as a re set pin regardless of which clk_div primitive is used. if a clock divider is used in the design, the cdrst pin is reserved and if it is driven high the clock divider is reset. if a reset port of a clock divider is not used, it is tied low on the board. the clock divider circuit includes an active high synchronous reset, referred to as cdrst. the coolrunner-ii cpld clock divider includes a built-in delay circuit. with the delay feature enabled, the output of the clock divider is delayed for one full count cycle. when used, the clock divider does not output a rising clock edge until after the divider reaches the delay value. the delay fea- ture is either enabled or disabled upon configuration. xilinx synthesis technology (xst) allows a clock divider component to be instantiated directly in the hdl source code. see xapp378 for instantiation examples in vhdl, verilog, and abel. dualedge each macrocell has the abilit y to double its input clock switching frequency. figure 9 shows the macrocell flip-flop with the dualedge option (doubled clock) at each macro- cell. the source to double can be a control term clock, a product term clock or one of the available global clocks. the ability to switch on both cloc k edges, also known as dual edge triggered (det), is vital for a number of synchronous memory interface applications as well as certain double data rate i/o applications. coolrunner-ii cpld det registers can be used for logic functions that include shift registers, counters, comparators, and state machines. designers must evaluate the desired performance of the cpld logic to determine use of det registers. the det register can be inferred in any abel, hdl, or schematic design. a designer can infer a single-edge trig- gered (set) register in any hdl design. the det register is available with all macrocells in all devices of the coolrunner-ii family. coolclock in addition to the dualedge flip-flop, power savings can occur by combining the clock division circuitry with the dualedge circuitry. this capability is called coolclock and is designed to reduce clocking power within the cpld. because the clock net can be an appreciable power drain, the clock power can be reduced by driving the net at half fre- quency, then doubling the clock rate using dualedge trig- gering at the macrocells. figure 10 shows how coolclock is created by internal clock cascading with the divider and dualedge flip-flop working together. gck2 is the only clock network that can be divided, the coolclock feature is only available on gck2. the cool- clock feature can be implemented by assigning an attribute to an input clock. the coolclock attribute replaces the need to instantiate the clock divider and infer det registers. the coolclock feature is available on coolrunner-ii 128 macrocell devices and larger. see xapp378 for more detail. figure 8: clock division circuitry for gck2 ds090_08_121201 clock in 2 4 6 8 10 12 14 16 gck2 cdrst cdrst
coolrunner-ii cpld family 10 www.xilinx.com ds090 (v3.1) september 11, 2008 product specification r design security designs can be secured during programming to prevent either accidental overwriting or pattern theft via readback. four independent levels of security are provided on-chip, eliminating any electrical or visual detection of configuration patterns. these security bits can be reset only by erasing the entire device. see wp170 for more detail. figure 9: macrocell clock chain with dualedge option shown figure 10: coolclock created by cascading cl ock divider and dualedge option gck0 gck1 gck2 clk_ct ptc ptc ds090_09_121201 d/t ce ck fif latch dualedge q ? gck0 gck1 gck2 ctc ptc ptc d/t ce ck fif latch dualedge q clock in 2 4 6 8 10 12 14 16 gck2 synch reset synch rst ?
coolrunner-ii cpld family ds090 (v3.1) september 11, 2008 www.xilinx.com 11 product specification r timing model figure 11 shows the coolrunner-ii cpld timing model. it represents one aspect of the overall architecture from a tim- ing viewpoint. each little block is a time delay that a signal incurs if the signal passes through such a resource. timing reports are created by tallying the incremental signal delays as signals progress within the cpld. software creates the timing reports after a design has been mapped onto the specific part, and knows the specific delay values for a given speed grade. equations for the higher level timing values (i.e., t pd and f system ) are available. ta bl e 6 summarizes the individual parameters and provides a brief definition of their associated f unctions. xilinx applic ation note xapp375 details the coolrunner-ii cpld family timing with several examples. figure 11: coolrunner-ii cpld timing model note: always refer to th e timing report in ise software for accurate timing values for paths. d/t s/r t f t sui t hi t coi t aoi t ecsu t echo t out t slew t en xapp375_03_010303 t oem t pdi t logi2 t logi1 t in t hys ce t din t hys t ct t gck t hys t gsr t hys t gts t hys ta bl e 6 : timing parameter definitions symbol parameter buffer delays t ln input buffer delay t din direct data register input delay t gck global clock (gck) buffer delay t gsr global set/reset (gsr) buffer delay t gts global output enable (gts) buffer delay t out output buffer delay t en output buffer enable/disable delay t slew output buffer slew rate control delay p-term delays t ct control term delay (single pt or fb-ct) t logi1 single p-term logic delay t logi2 multiple p-term logic delay adder macrocell delays t pdi macrocell input to output valid t sui macro register setup before clock t hi macro register hold after clock t ecsu macro register enable clock setup time t echo macro register enable clock hold time t coi macro register clock to output valid t aoi macro register set/reset to output valid t hys hysteresis selection delay adder feedback delays t f feedback delay t oem macrocell to global oe delay ta b l e 6 : timing parameter definitions (continued) symbol parameter
coolrunner-ii cpld family 12 www.xilinx.com ds090 (v3.1) september 11, 2008 product specification r programming the programming data sequence is delivered to the device using either xilinx impact software and a xilinx download cable, a third-party jtag development system, a jtag-compatible board tester, or a simple microprocessor interface that emulates the jtag instruction sequence. the impact software also outputs serial vector format (svf) files for use with any tools that accept svf format, including automatic test equipment. see coolrunner-ii cpld application notes for more information on how to program. in system programming all coolrunner-ii cpld parts are 1.8v in system program- mable. this means they derive their programming voltage and currents from the 1.8v v cc (internal supply voltage) pins on the part. the v ccio pins do not participate in this operation, as they might assume another voltage ranging as high as 3.3v down to 1.5v (however, all v ccio , v ccint , v ccaux , and gnd pins must be connected for the device to be programmed, and operate correctly). a 1.8v v cc is required to properly operate the internal state machines and charge pumps that reside within the cpld to do the nonvol- atile programming operations. i/o pins are not in user mode during jtag programming; they are held in 3-state with a weak pullup. the jtag interface buffers are powered by a dedicated power pin, v ccaux , which is independent of all other supply pins. v ccaux must be connected. xilinx soft- ware is provided to deliver the bitstream to the cpld and drive the appropriate ieee 1532 protocol. to that end, there is a set of ieee 1532 commands that are supp orted in the coolrunner-ii cpld parts. programming times are less than one second for 32 to 256 macrocell parts. program- ming times are less than four seconds for 384 and 512 mac- rocell parts. programming of coolrunner-ii cplds is only guaranteed when operating in the commercial temperature and voltage ranges as defined in the device-specific data sheets. on-the-fly reconfiguration (otf) the xilinx ise 5.2i tool supp orts otf for coolrunner-ii cplds. this permits progra mming a new nonvolatile pat- tern into the part while another pattern is currently in use. otf has the same voltage and temperature specifications as system programming. during pattern transition i/o pins are in high impedance with a weak pullup to v ccio . transi- tion time typically lasts between 50 and 300 s, depending on density. see xapp388 for more information. jtag instructions ta bl e 7 shows the commands available to users. these same commands can be used by third party ate products, as well. the internal controllers can operate as fast as 66 mhz. power-up characteristics coolrunner-ii cpld parts must operate under the demands of both the high-speed and the portable market places; therefore, they must support hot plugging for the high-speed world and tolerate most any power sequence to its various voltage pins. they must also not draw excessive current during power-up initialization. to those ends, the general behavior is summarized as follows: 1. i/o pins are disabled until the end of power-up. 2. as supply rises, configuration bits transfer from nonvolatile memory to sram cells. 3. as power up completes, the outputs become as configured (input, output, or i/o). 4. for specific configuration times and power up requirements, see x app389 . coolrunner-ii cpld i/o pins are well behaved under all operating conditions. during power-up, coolrunner-ii devices employ internal circuitry which keeps the devices in the quiescent state until the v ccint supply voltage is at a safe level (approximately 1.3v). in the quiescent state, jtag pins are disabled, and all device outputs are disabled with the pins weakly pulled high, as shown in ta b l e 8 . when the supply voltage reaches a safe level, all user registers become initialized, and the device is immediately available for operation, as shown in figure 12 . best results are obtained with a smooth v cc rise in less than 4 ms. final v cc value should occur within 1 second. if the device is in the erased state (before any user pattern is programmed), the device outputs remain disabled with a weak pull-up. the jtag pins are enabled to allow the device ta b l e 7 : jtag instructions code instruction description 00000000 extest force boundary scan data onto outputs 00000011 preload latch macrocell data into boundary scan cells 11111111 bypass insert bypass register between tdi and tdo 00000010 intest force boundary scan data onto inputs and feedbacks 00000001 idcode read idcode 11111101 usercode read usercode 11111100 highz force output into high impedance state 11111010 clamp latch present output state
coolrunner-ii cpld family ds090 (v3.1) september 11, 2008 www.xilinx.com 13 product specification r to be programmed at any time. all devices are shipped in the erased state from the factory. applying power to a blank part might result in a higher cur- rent flow as the part initializes . this behavior is normal and might persist for approximately 2 seconds, depending on the power supply ramp. if the device is programmed, the device inputs and outputs take on their configured states for normal operation. the jtag pins are enabled to allow device erasure or bound- ary-scan tests at any time. i/o banking coolrunner-ii cpld xc2c32a and xc2c64a macrocell parts support two v ccio rails that can range from 3.3v down to 1.5v operation. two v ccio rails are supported on the 128 and 256 macrocell parts where outputs on each rail can independently range from 3.3v down to 1.5v operation. four v ccio rails are supported on the 384 and 512 macro- cell parts. any of the v ccio rails can assume any one of the v ccio values of 1.5v, 1.8v, 2.5v, or 3.3v. designers should assign input and output voltages to a bank with v ccio set at the voltage range of that input or output voltage. the v cc (internal supply voltage) for a coolrunner-ii cpld must be maintained within 1.8v 5% for correct speed operation and proper in system programming. mixed voltage, power sequencing, and hot plugging as mentioned in i/o banking, coolrunner-ii cpld parts support mixed voltage i/o signals. it is important to assign signals to an i/o bank with the appropriate i/o voltage. driv- ing a high voltage into a low vo ltage bank can result in neg- ative current flow through the power supply pins. the power applied to the v ccio and v cc pins can occur in any order and the coolrunner-ii cpld will not be damaged. for best results, xilinx recommends that v ccint be applied before v ccio to ensure that the internal logic is correct before the i/os are active. coolrunner-ii cplds can reside on boards where the board is inserted into a ?live? connector (hot plugged) and the parts will be well-behaved as if powering up in a standard way. development system support xilinx coolrunner-ii cplds are supported by all configura- tions of xilinx standard rele ase development software as well as the freely available ise webpack software avail- able from www.xilinx.com . third party development tools include synthesis tools from cadence, exemplar, mentor graphics, synplicity, and synopsys. ate support third party ate development support is available for both programming and board/chip level testing. vendors provid- ing this support include agilent, genrad, and teradyne. other third party providers are expected to deliver solutions in the future. figure 12: device behavior during power up v ccint no power 3.8 v (typ) 0v no power quiescent state quiescent state user operation initialization transition of user array x382_10 1.3v (typ) ta bl e 8 : i/o power-up characteristics device circuitry quiescent state erased device operation valid user operation iob bus-hold/weak pullup weak pull-up weak pull-up bus-hold/weak pullup device outputs disabled disabled as configured device inputs and clocks disabled disabled as configured function block disabled disabled as configured jtag controller disabled enabled enabled
coolrunner-ii cpld family 14 www.xilinx.com ds090 (v3.1) september 11, 2008 product specification r absolute maximum ratings quality and reliability parameters warranty disclaimer these products are subject to the terms of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of the products in an application or environment that is not within the specifications stated on the then-current xilinx data sheet for the products. products are not designed to be fail-safe and are not warranted for use in applications that pose a risk of physical harm or loss of life. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations. further reading application notes http://www.xilinx.com/support/documenta- tion/application_notes/xapp784.pdf (bulletproof design practices) http://www.xilinx.com/support /documentation/application_no tes/xapp375.pdf (timing model) http://www.xilinx.com/support /documentation/application_no tes/xapp376.pdf (logic engine) http://www.xilinx.co m/support/documenta- tion/application_notes/xapp317.pdf (power evaluation equation for coolrunner-ii cplds) http://www.xilinx.co m/support/documentation/application_no tes/xapp377.pdf (low power design) http://www.xilinx.co m/support/documentation/application_no tes/xapp378.pdf (advanced features) http://www.xilinx.co m/support/documentation/application_no tes/xapp379.pdf (high speed design) http://www.xilinx.co m/support/documentation/application_no tes/xapp380.pdf (cross point switch) symbol parameter ( 1 ) min. max. unit v cc ( 2 ) supply voltage relative to gnd ?0.5 2.0 v v i ( 3 ) input voltage relative to gnd ?0.5 4.0 v t a ambient temperature (c-grade) 0 70 c ambient temperature (i-grade) ?40 85 c t j ( 4 ) maximum junction temperature ?40 150 c t str storage temperature ?65 150 c notes: 1. stresses above those listed might cause ma lfunction or permanent damage to the device. this is a stress rating only. function al operation at these or any other condition above those indicated in the operational a nd programming specification is not implied . 2. the chip supply voltage should rise monotonically. 3. maximum dc undershoot below gnd must be lim ited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, the device pins might undershoot to ?2.0v or overshoot to 4.5 v, provided this overshoot or undershoot lasts less than 10 ns and wi th the forcing current being limited to 200 ma. the i/o voltage can never exceed 4.0v. 4. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb-free packages, see xapp427 . symbol parameter min max units t dr data retention 20 - years n pe program/erase cycles (endurance) 1,000 - cycles v esd electrostatic discharge(1) 2,000 - volts notes: 1. esd is measured to 2000v using the human body model. pins exposed to this limit can incur additional leakage current to a maximum of 10 a when driven to 3.9v.
coolrunner-ii cpld family ds090 (v3.1) september 11, 2008 www.xilinx.com 15 product specification r http://www.xilinx.com/support /documentation/application_no tes/xapp381.pdf (demo board) http://www.xilinx.com/support /documentation/application_no tesxapp382.pdf (i/o characteristics) http://www.xilinx.com/support /documentation/application_no tes/xapp383.pdf (single error correction double error detection) http://www.xilinx.com/support /documentation/application_no tes/xapp384.pdf (ddr sdram interface) http://www.xilinx.com/support /documentation/application_no tes/xapp387.pdf (picoblaze microcontroller) http://www.xilinx.com/support /documentation/application_no tes/xapp388.pdf (on the fly reconfiguration) http://www.xilinx.com/support /documentation/application_no tes/xapp389.pdf (powering coolrunner-ii) http://www.xilinx.com/support /documentation/application_no tes/xapp393.pdf (8051 microcontroller interface) http://www.xilinx.com/support /documentation/application_no tes/xapp394.pdf (interfacing with mobile sdram) http://www.xilinx.com/support /documentation/application_no tes/xapp399.pdf (assigning coolrunner-ii vref pins) coolrunner-ii cpld data sheets http://www.xilinx.com/suppor t/documentatio n/data_sheets/d s090.pdf (coolrunner-ii family data sheet) http://www.xilinx.com/suppor t/documentatio n/data_sheets/d s310.pdf (xc2c32a data sheet) http://www.xilinx.com/suppor t/documentatio n/data_sheets/d s311.pdf (xc2c64a data sheet) http://www.xilinx.com/suppor t/documentatio n/data_sheets/d s093.pdf (xc2c128 data sheet) http://www.xilinx.com/suppor t/documentatio n/data_sheets/d s094.pdf (xc2c256 data sheet) http://www.xilinx.com/support/documentation/data_sh eets/ds095.pdf (xc2c384 data sheet) http://www.xilinx.com/suppor t/documentatio n/data_sheets/d s096.pdf (XC2C512 data sheet) coolrunner-ii cpld white papers http://www.xilinx.co m/support/documenta- tion/white_papers/wp170.pdf (secure applications) packages package drawings revision history the following table shows the revision history for this document. date version revision 01/03/02 1.0 initial xilinx release 07/04/02 1.1 revisions and updates 07/24/02 1.2 revisions and updates 09/24/02 1.3 additions to "power characteristics" section 01/28/03 1.4 addition of the "further reading" section 02/26/03 1.5 multiple minor revisions 03/12/03 1.6 minor revision to "q uality and reliability parameters" 10/09/03 1.7 update hewlett-packard to agilent, ofr to otf, and other revisions 01/26/04 1.8 incorporate links to data sheets, application notes, and device packages 02/26/04 1.9 change to power-up characteristics, page 11. change t fin to t din . add schmitt-trigger i/o compatibility info rmation. added t sol specification. 05/21/04 2.0 add xc2c32a and xc2c64a devices. 07/30/04 2.1 pb-free documentation. changes to t su and f system to match individual data sheets. 01/10/05 2.2 added information about programming options, page 11. 03/07/05 2.3 changes to table 1, t pd , t su , t co , and f system1. removed link to obsolete white paper. modifications to table 5, iostandards. added table 2, dc characteristics.
coolrunner-ii cpld family 16 www.xilinx.com ds090 (v3.1) september 11, 2008 product specification r 04/15/05 2.4 change to f system1 for xc2c128. 06/28/05 2.5 move to product specification 03/20/06 2.6 add warranty disclaimer; modified global signals section to say that gck, gsr and gts can be used as general purpose i/o. 07/24/06 2.7 change to hot plugging recommendations, page 13 (v ccint before v ccio power sequencing). 12/7/06 2.8 add description of i/o pin status during jtag programming, page 12. add note about power pins during programming. add link to application note 389, page 12. added clarification to clock divider description, page 9. 02/15/07 2.9 add greater description to advanced features. added ambient temperature specification. 03/08/07 3.0 add link to power estimation appnote, page 14. 09/11/08 3.1 removed reference to xc2c32 and xc2c64 devices. see product discontinuation notice xcn05017.pdf . removed references to pc44 and pcg44 packages. see product discontinuation notice xcn07022.pdf . date version revision

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